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INTELLECTUAL PROPERTIES

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PCI - X 2.0

Introduction

The ASIC division of DCM Technologies Ltd., a PCI-SIG member, has been a front-runner in the PCI/PCI-X domain. Highly experienced professionals with strong knowledge of PC internals manage the group. The strength in PCI/PCI-X comes obviously to a group that has worked on several ISA, EISA bus based designs in the past.

PCI-X 2.0 Mode - 2 IP

Features

  • Written in Verilog RTL
  • Mode-1 (133) PCI-X Re vision 2.0
    • FPGA 100 MHz PCI-X only
    • ASIC 33 MHz PCI, 133 MHz PCI-X
  • Mode-2 (266) PCI-X Revision 2.0
    • ASIC 266 MHz operation, subject to availability of PCI-X 2.0 I/O pads
  • User Logic Interface (ULI) provides
    • 32/64 Bit interface for PCI-X 2.0 Mode-1
    • 128 Bit interface for PCI-X 2.0 Mode-2
  • Can be used in Controller mode or Bridge (Primary/Secondary/Host) mode
  • Highly parameterized for adapting to any application
  • Targeted to CMOS DSM ASIC library

PCI-X 2.0 Mode - 2 Verification IP

Features

  • Written in Verilog
  • The BFM supports
    • PCI Revision 2.3
    • PCI-X Revision 2.0a
    • PCI-X 266 and PCI-X 533
    • DIM & ECC in Mode 1 & Mode 2
    • 32/64 bit transactions support
  • Scalable to instantiate multiple components allowing complex Bus hierarchy
  • Task based invocation for a user friendly interface
  • Supports simulation break on defined error or programmable error count
  • Time critical functions handling using C- based PLI enhancing simulation time
  • Supports multiple outstanding transactions
  • Supports multiple outstanding split completion transactions
  • Protocol Error / Fault insertion
  • User Defined Event-trigger (UDE) generation
  • Multiple Memory/IO/DIM regions support
  • Option for priority/order based arbitration
  • Bus Monitor for protocol compliance
  • Logging of PCI-X transaction sequence
  • Setup & Hold time checks useful in gate level simulation
  • Option for Path delay assertion on bus signals
  • Error based simulation halt

PCI-X 2.0 Mode - 1 IP

CoreX-V21 is a high performance, flexible, synthesizable core that implements PCI(X) Initiator/Target. The Verilog core is suitable for FPGA and ASIC applications and is available in Source code and netlist formats.

PCI-X 2.0 Mode - 1 Verification IP

In order to reduce your time-to-market further, DCM offers a ready-to-use PCI-X Verification environment. This environment enables the user to initiate and receive PCI-X cycles to/from the user logic. This pre-tested environment is comprised of PCI-X Master, Target Bus Functional Models (BFM), a PCI-X Bus Monitor along with a PCI-X Bus Arbiter.

DCM also provides Services for the smooth integration of these IPs into actual customer designs.

 
 
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